1. Field of the Invention
The invention relates generally to a mask used in the manufacture of semiconductor wafers. More particularly, the invention relates to a mask having a modified topography to facilitate optical proximity correction with minimal effect on the semiconductor wafer.
2. Description of the Related Art
Masks used in the fabrication of semiconductor wafers define topography. The topography changes, alters and/or blocks light passing therethrough in the creation of the semiconductor wafer. Optics are used to focus light as it is sent through the mask to make smaller images on the semiconductor wafer allowing the semiconductor wafer to be formed in the image of the mask. While the optics are very precise, the physics of producing a semiconductor wafer with such small dimensions results in discrepancies between the topographies of the mask and the semiconductor wafer to the extent that modifications to the mask topography will aid in creating the semiconductor wafer with the desired topography.
Optical proximity correction (OPC) is a proven technique that facilitates the fabrication of a semiconductor wafer with a topography that is desired. OPC designs are created through an iterative process that models the topography of a mask and predicts how much of the topography of the semiconductor wafer will mirror what is actually desired out of its topography. The mask topography changes from the “ideal” topography to compensate for the properties of the light, optics and materials being used.
Along with OPC, cornering is a method used to reduce the critical dimension (CD) of elements formed on a semiconductor wafer. By rounding the corners, the dose required to create a feature or element is reduced. In other words, the CD of a semiconductor wafer is reduced given a fixed dose. By incorporating the methods of OPC and rounding of corners, the CD of the semiconductor wafer can be reduced.
Yet another method of increasing the CD on a semiconductor wafer is to taper mask edges. U.S. Pat. No. 6,399,286 discloses a method for fabricating a semiconductor wafer wherein the CD of the semiconductor wafer is reduced by tapering edges of elements in the mask layer. This mask is not, however, designed to minimize the number of elements created on the semiconductor wafer as compared to the number of elements fabricated on the mask.